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10 3
MC [ imp/kwh ] × 10 n
CFCYC = 2
ADE7854/ADE7858/ADE7868/ADE7878
By default, the TERMSELx bits are all 1 and the CF1SEL bits are
000, the CF2SEL bits are 001, and the CF3SEL bits are 010. This
means that by default, the CF1 digital-to-frequency converter
produces signals proportional to the sum of all 3-phase total
active powers, CF2 produces signals proportional to total
reactive powers, and CF3 produces signals proportional to
apparent powers.
Similar to the energy accumulation process, the energy-to-
frequency conversion is accomplished in two stages. In the first
stage, the instantaneous phase powers obtained from the DSP at
the 8 kHz rate are shifted left by seven bits and then accumulate
into an internal register at a 1 MHz rate. When a threshold is
reached, a pulse is generated and the threshold is subtracted
from the internal register. The sign of the energy in this moment
is considered the sign of the sum of phase powers (see the Sign
of Sum-of-Phase Powers in the CFx Datapath section for details).
The threshold is the same threshold used in various active,
reactive, and apparent energy accumulators in the DSP, such
as the WTHR, VARTHR, or VATHR registers, except for being
shifted left by seven bits. The advantage of accumulating the
instantaneous powers at the 1 MHz rate is that the ripple at the
CFx pins is greatly diminished.
The second stage consists of the frequency divider by the
CFxDEN 16-bit unsigned registers. The values of CFxDEN
depend on the meter constant (MC), measured in impulses/kWh
and how much energy is assigned to one LSB of various energy
registers: xWATTHR, xVARHR, and so forth. Supposing a deri-
vative of wh [10 n wh], n a positive or negative integer, is desired
as one LSB of xWATTHR register. Then, CFxDEN is as follows:
CFxDEN = (46)
The derivative of wh must be chosen in such a way to obtain a
CFxDEN register content greater than 1. If CFxDEN = 1, then
the CFx pin stays active low for only 1 μs, therefore, avoid this
number. The frequency converter cannot accommodate fractional
results; the result of the division must be rounded to the nearest
integer. If CFxDEN is set equal to 0, then the ADE78xx considers it
to be equal to 1.
The pulse output for all digital-to-frequency converters stays
low for 80 ms if the pulse period is larger than 160 ms (6.25 Hz). If
the pulse period is smaller than 160 ms and CFxDEN is an even
number, the duty cycle of the pulse output is exactly 50%. If the
pulse period is smaller than 160 ms and CFxDEN is an odd
number, the duty cycle of the pulse output is
(1+1/ CFxDEN ) × 50%
Data Sheet
The pulse output is active low and preferably connected to an
LED, as shown in Figure 76.
V DD
CFx PIN
Figure 76. CFx Pin Recommended Connection
Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE
register decide if the frequency converter output is generated
at the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the
default value), the CFx pin is disabled and the pin stays high.
When Bit CFxDIS is cleared to 0, the corresponding CFx pin
output generates an active low signal.
Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask Register MASK0
manage the CF3, CF2, and CF1 related interrupts. When the
CFx bits are set, whenever a high-to-low transition at the corres-
ponding frequency converter output occurs, an interrupt IRQ0
is triggered and a status bit in the STATUS0 register is set to 1.
The interrupt is available even if the CFx output is not enabled
by the CFxDIS bits in the CFMODE register.
Synchronizing Energy Registers with CFx Outputs
The ADE7854 / ADE7858 / ADE7868 / ADE7878 contain a feature
that allows synchronizing the content of phase energy accu-
mulation registers with the generation of a CFx pulse. When
a high-to-low transition at one frequency converter output
occurs, the content of all internal phase energy registers that
relate to the power being output at CFx pin is latched into hour
registers and then resets to 0. See Table 22 for the list of registers
that are latched based on the CFxSEL[2:0] bits in the CFMODE
register. All 3-phase registers are latched independent of the
TERMSELx bits of the COMPMODE register. The process is
shown in Figure 77 for CF1SEL[2:0] = 010 (apparent powers
contribute at the CF1 pin) and CFCYC = 2.
The CFCYC 8-bit unsigned register contains the number of high to
low transitions at the frequency converter output between two
consecutive latches. Avoid writing a new value into the CFCYC
register during a high-to-low transition at any CFx pin.
CF1 PULSE
BASED ON
PHASE A AND
PHASE B
APPARENT
POWERS
AVAHR, BVAHR, AVAHR, BVAHR,
CVAHR LATCHED CVAHR LATCHED
ENERGY REGISTERS ENERGY REGISTERS
RESET RESET
Figure 77. Synchronizing AVAHR and BVAHR with CF1
Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the
CFMODE register enable this process when set to 1. When
cleared to 0, the default state, no latch occurs. The process is
available even if the CFx output is not enabled by the CFxDIS
bits in the CFMODE register.
Rev. H | Page 62 of 100
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